The increased speed of modern digital circuits requires highly accurate techniques for timing analysis so that the circuit designs can be adequately tested and verified. Timing analysis, in general, refers to the process of calculating signal arrival times at clock-controlled nodes of a circuit design to verify that the signal will arrive at each node within a specified time interval. For instance, for an edge triggered register, the signal must arrive at the register before the active edge of the clock. If the signal does not arrive within the specified timing interval, a violation occurs, potentially causing the circuit to malfunction.
Typically, timing analysis is performed using an Electronic Design Automation (EDA) tool. The EDA tool essentially analyzes a digital circuit, which can be expressed using a hardware description language (HDL), as well as a timing description of the digital circuit. In general, there are two different types of timing analysis that can be performed. One is called dynamic timing analysis and the other is called static timing analysis.
Within dynamic timing analysis, a delay annotation tool accesses a collection of fixed delays that model various timing parameters of the digital circuit. An example of a dynamic timing simulation program is the Xilinx® ISE Simulator, also known as “Isim,” which is commercially available from Xilinx, Inc. of San Jose, Calif. Xilinx, ISE, and Isim are trademarks of Xilinx, Inc. in the United States, other countries, or both. In general, Isim is an HDL simulator capable of performing functional and timing simulations for VHDL and Verilog designs. Typically, timing information is specified within a Standard Delay Format (SDF) file as defined by Open Verilog International. Input vectors are provided to the circuit design under test.
The delays specified in the SDF file are fixed in that each represents a timing parameter of the digital circuit under a different set of physical circumstances relating to manufacturing process, temperature, voltage, etc. The fixed delays specified in the SDF file represent delays associated with different components of the digital circuit under what can be considered extreme operating conditions. While the delay information used for dynamic timing analysis covers a range of scenarios, it does not reflect variations in conditions that occur during normal operation of the digital circuit.
By comparison, static timing analysis performs more complex timing calculations and requires no input vectors. Static timing analysis can evaluate all possible paths of a digital circuit, and can indicate a worst case scenario in terms of the delay information that is created on a per signal path basis. As such, static timing analysis reflects the delay variations that may occur during normal operation of a digital circuit. Examples of these variations can include, but are not limited to, clock skew, clock uncertainty, or the like.
In general, static timing analysis involves two types of analysis. The first type of analysis, referred to as a “setup check,” determines the maximum delay of a path to a synchronous circuit element. A setup check determines the latest time a data signal can arrive at the input port of a destination register before a timing violation, called a setup violation, occurs. The second type of static analysis, referred to as a “hold check,” concerns determining a minimum delay of a path in the circuit design. A hold check determines whether a data signal at an input port of a given clocked circuit element is stable, e.g., remains constant, for a long enough time period. If not, a timing violation called a hold violation occurs.
In view of the differences between dynamic and static timing analysis, there often are differences between the results obtained using dynamic timing analysis and the results obtained using static timing analysis for the same digital circuit. For example, the timing information used in dynamic timing analysis may be overly optimistic with respect to the signal path delays used.